# Simple Sawtooth VCO

So I’m looking to do some analogue synthesizer design and one of the coolest sounding basic waveforms for a synthesizer (imo, of course) is the sawtooth wave. The sawtooth wave is pretty much described by its name – a wave that increases linearly then drops off as fast as possible, as if to imitate the tooth of a saw.

Sawtooth waves are used heavily in subtractive synthesis due to their high harmonic content allowing for creative modelling to be applied through filtering etc. because of this, they along with a square, triangle and sine wave are generally the staple of basic synthesizer waveforms.

There are quite a few methods for generating a sawtooth wave though the method I’ve decided to use is modifying a standard relaxation oscillator to control a current source during the charging of a capacitor and providing a diode for the discharge path to provide fast edges. Using a standard two op amp IC (Microchip MCP6002), two transistors (BC327), a Diode (1N4148) and a handful of passive components (100nF cap, 10nF cap, 2x 10k resistors, 2x 1k resistors and a 100k resistor), I was able to test my design and get some performance metrics of such a simple circuit. Simulations were obtained from LTSpice to assess the linearity of voltage to frequency control

Simulation results
The circuit was simulated in LTSpice and the output frequency was obtained using the FFT functionality of LTSpice. The charging current is essentially equal to the current flowing through R3. If Q2 is assumed to be a diode connected transistor (it essentially is) with a constant forward voltage of 0.6V, the current through R3 is merely:

(V-(0.6 + VCtrl))/100k = Ic.

It can be seen from the above equation that increasing VCtrl will decrease the charging current and therefore decrease the frequency. If the falling edge can be assumed to be instantaneous (in reality, it was measured at 4.55us), the frequency of operation can be assumed to be the time taken to linearly charge the capacitor from V+/4 to 3V+/4, where V+ is equal to 3V. Rearranging the standard equation for current through a capacitor I = CdV/dT to make dT the subject gives:

dT = CdV/I

dTt = CdV/I + Tfall

F = 1/(CdV/I + Tfall)

F = 1/(10n*(3*3/4 – 3/4)/((3 – (0.6 + VCtrl))/100k) + Tfall)

Testing this with a few values gives a general approximation of the output and using Tfall can further increase the accuracy of the frequency to voltage relationship. For the values given in the above schematic, assuming zero fall time, the output frequencies for a small range of values are:

0V: 1.6kHz
1V: 933.3Hz
2V: 266.7Hz

Comparing these values to the simulation results of:

0V: 1.64kHz
1V: 989Hz
2V: 358Hz

Shows a small error. This is probably due to the fact the current sources are non-ideal and the forward voltage drop of the diode connected transistor isn’t always a constant 0.6V.

Using the simulation results, a curve fit equation for frequency which accounts for some of the physical component discrepancies could be:

F = 641.02*VCtrl + 1636.7

Real Circuit
Obviously building this on a breadboard isn’t that hard and can be done with thanks to the few components required. Issues arise however with the transistor current mirror and not using matched transistors – especially under wide operating temperature ranges! In my cold room (probably 13-14 degrees?), using components with tolerances ~10% (resistors) and ~20% (capacitors), I was able to match the simulation results with a maximum of 12.03% error. The results found for the physical circuit were:

0V: 1.83kHz – 11.59% Error
1V: 1.108kHz – 12.03% Error
2V: 385.6kHz – 7.72% Error

However, these frequencies varied massively if I heated up the current mirror transistors proving this section to be insufficient for good temperature independent performance. Changing this stage could increase stability along with using much lower tolerance components. It does however produce a pretty good sawtooth wave with constant amplitude over a relatively wide range of frequencies!