Altera Cyclone IV FPGA Board – Schematic
A couple of people requested the pinout that I’ve used for my board, I’ve uploaded this below. Cyclone4 FPGA Boardschematic_v200
A couple of people requested the pinout that I’ve used for my board, I’ve uploaded this below. Cyclone4 FPGA Boardschematic_v200
In my last post, I was talking about image compression methods, mainly DCT transform based along with colour transform based. I’ve now combined these together and have managed to break the 6fps barrier for video over UART! I’ve implemented 2:1:1, 4:1:1 and 8:1:1 subsampling (I think I can call it that?) with reasonable performance! The […]
Image compression is a massive topic and to be honest, a bit of a buzzword title. Images can be compressed in multiple ways. One of the simplest being reducing the bit depth of the image. Reducing the bit depth is a pretty poor method of compression though and generally produces weird banding results as could […]
As of yesterday, I’ve got a new laptop (woop woop I7-7700HQ)! Obviously that meant transferring data over though a bit of WiFi and an overnight transfer deemed me ready to rock this morning. I do however have an exam in a week which I should probably start revising for so this will be my last […]
As I mentioned in my last post, I wanted to try some image segmentation! I had a quick go at histogram based segmentation where the largest peak of the histogram was used to find the most occuring pixel (after the colour range was bit crushed) but this didn’t have particularly useful results. This could be […]
One of the staples of image processing is edge detection. Edge detection is generally one of the primary steps for further image processing methods including feature detection. Conceptually, edge detection is relatively simply. Look at the image and compare areas of low intensity to areas of high intensity, simple right? Actually yeh, it is that […]
What do you get when you combine an FPGA with some SDRAM and an OV7670 camera, transferring uncompressed frames through UART? Really poor performance, reliability and a pretty useless end product… Though just because it sucks that doesn’t mean it isn’t worth doing! I’ve had my first exam and I’ve wanted to crack on with […]
Mandlebrot Set Generator As I said in my last post, I implemented a Mandlebrot set generator in my STM32. Even though it was running at 64MHz, generating the set took a fair bit of time, slow enough to not even maximise the fully available SDRAM capacity at the time. At this point, I decided to […]
So I did this project a looooong time ago (Actually around this time last year…..) where my FPGA was acting as a video controller for the STM32F0. I’ve recently improved (or I’d like to think I have given my final year project) my VHDL skills so I thought I’d give this another shot. I completely rewrote […]
So today has been exceptional! I’ve made loads of progress with thanks to the arrival of my new components. As was stated previously, there were way too many losses in the gate shift registers using the 4x 1k resistor arrays. Therefore, I needed to replace the arrays for 1k resistors to the gate (maximum output […]