SSD1306 VHDL FPGA Implementation

I’ve been reading up as much VHDL as possible these last few days as I’ve recently found out that the majority of my summer is going to consist of writing it! After seeing loads of implementations for HD44780 16×2 character based LCDs, I couldn’t find any examples for the easy to get LCDs (by easy, […]

Altera CPLD development board

Well! I’ve been looking to further develop my VGA controller on my CPLD. So as per, I’ve been researching into methods and what not and found out that 800×600 at a refresh rate of 72Hz uses a standard pixel clock of 50MHz! This is obviously in comparison to many other VGA modes which seem to […]