CPLD Fun – SPI Master data transmitter

So today, I had my first lecture on VHDL. I’m not a massive fan of learning to code through lectures without doing but we have labs on it later in the year. I would by no matter consider myself a pro at VHDL coding but I’d like to think I have the slight grasps after designing a few projects. So today, I decided to have a go at designing the simplest SPI master data transmitting controller. This could be coupled with a simple SPI dac (such as the PT8211) to produce simple waveforms and currently only operates in CPOL=0 and CPHA=0 mode. Fortunately, this is the most common mode and is used among most devices. My version has a simple prescalar allowing for integer power of 2 divisions of the master clock (1, 4, 8, 16, 32, 64, etc.). Every clock is sent after two prescale cycles meaning that the SPI output clock frequency will be equal to (MasterClock/(Prescaler))/2.

For a quick test example, I’ve used a prescalar of 2^7 = 128. The prescaler works by incrementing a “variable” (signal) and everytime it overflows to zero, executing the simple SPI state machine. with a 50MHz clock, this should produce an SPI clock of (50M/128)/2 = ~195kHz. Viewing this with my logic analyzer confirms this! As a quick test, I’m incrementing the data being sent by one after every transmission to ensure it is sending correctly.

Looking at the frequency in the right hand measurement pane concludes a frequency of ~195kHz, good so far!

As can be seen in the image above, the data is successfully incrementing everytime. The MISO line isn’t connected to anything as MISO isn’t implemented yet. As you can also see in the logic diagram, the data being sent each transmission gets incremented too showing that section is correct! You can also see here that the enable pulse is as long as the SPI clock pulse. This is because the enable pulse is defined by the state machine using the same prescaler as the SPI clock. My version doesn’t actually use standard VHDL state machines and is implemented using a state counting variable and a few if statements.

My trusty CPLD development board wired up to the byte blaster and my logic analyzer. Long live Hobby Components!

In other news, I’ve also purchased a proper FPGA development board based on the EP4CE6E22C8N (http://goo.gl/lFhJIX – Link will expire!) so hopefully, I can get round to programming some pretty intense VHDL stuffs. In the meanwhile however, I’ll be sticking with this board until the next one arrives!

The code isn’t particularly hard but it can still be found on my Pastebin!

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